Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones and others. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual devices. Smaller devices can operate at higher speeds since the physical distance between components is smaller. In addition, higher conductivity materials, such as copper, are replacing lower conductivity materials, such as aluminum. One other challenge is to increase the mobility of semiconductor carriers such as electrons and holes.
One technique to improve transistor performance is to strain (i.e., distort) the semiconductor crystal lattice near the charge-carrier channel region. Transistors built on strained silicon, for example, have greater charge-carrier mobility than those fabricated using conventional substrates. One technique to strain silicon is to provide a layer of germanium or silicon germanium. A thin layer of silicon may be grown over the germanium-containing layer. Since the germanium crystal lattice is larger than silicon, the germanium-containing layer creates a lattice mismatch stress in adjacent layers. Strained channel transistors may then be formed in the strained silicon layer.
Another technique is to provide a stress layer over the transistor. Variants of stress layers can be used for mobility improvement and performance boost of devices. For example, stress can be provided by a contact etch stop layer (CESL), single layers, dual layers, stress memory transfer layers, STI liners, and CA liners. Most of these techniques use nitride layers to provide tensile and compressive stresses; however, other materials can be used in other applications, e.g., HDP oxide layers.
Another method for inducing strain, known as embedded SiGe (eSiGe), involves creating a recess in the source and drain regions of a MOS transistor and growing a doped SiGe film within the recess in lieu of a conventional silicon source and drain region. The larger germanium crystal lattice creates a stress in the channel between the source and drain and thereby enhances the carrier mobility. Typically, the higher the Ge concentration in the SiGe film grown within the recesses, the higher the carrier mobility that can be achieved.
In the field of small, densely packed applications using small geometry CMOS transistors, however, the use of eSiGe to enhance carrier mobility becomes challenging because as the geometries of the semiconductor process get smaller, higher stress is required in the channel in order to maintain adequate performance. While increasing the concentration of Ge in the SiGe film is desirable to achieve this goal, manufacturing a high yield SiGe film with a higher and higher Ge concentration becomes progressively more difficult.